Serial buses are known in the prior art. Examples of serial buses include USB, HDMI, DVI, and SATA buses. In prior art serial buses, when the serializer, TX, and deserializer, RX, are used for serial data communication, the circuits must synchronize between TX and RX through communicating a set of protocols to establish a synchronized state before starting data transfer. The synchronization process includes tasks such as equalization, clock recovery, type of transfer, length of data transfer, client identification, cyclic redundancy check, master request, client grant, and other system predefined tasks. Due to the nature of serial link communication, this synchronization cannot be done by adding extra physical wires of side band bus to reduce power consumption or to shorten the latency. Traditionally, such side band communication is implemented within existing serial physical wires by partitioning the transfer cycle into transfer header sessions (side band bus communication) and transfer block data sessions (data bus communication). This type of side band communication bus implementation results in not only high power consumption but also long latency of data transfer due to the fact that side band communication must occupy a portion of the total transfer time in serial link communication and serial link must be in full power to perform the transfer header sessions. Side band communication often consumes 20-30% of the total transfer time. Data cannot be transferred during that period, which is a significant limitation of prior art serial buses.